Date: Thursday April 9, 2015
Time: 9:00AM - 1:00PM
UCSC Silicon Valley Extension
2505 Augustine Dr
Santa Clara, CA 95054
Presented by: Tony Smith
Breakfast and lunch will be provided
Pre-work: Come prepared to tackle your next timing tree design! Bring a laptop and learn how to customize a timing solution purpose-built for your application. NOTE: Install ClockBuilderPRO™ at www.silabs.com/clockbuilderpro. The presenter will walk through the demonstrations and exercises for those that are unable to bring a laptop.
9:00 Introductions. Purpose/Plan for JITTER SMACKDOWN
9:15 What is JITTER?
- Why is it ruining my life?
- Best practices to reduce Jitter
- Best practices for measuring PCIe Jitter
What is PSRR and why is that important in timing?
9:45 Demo 1: Jitter/PSRR measurement
10:30 Intro to timing trees
- Growing complexity industry trends
- Existing solutions. Typical Engineering approach to selecting timing tree
- New products that Keep Your Timing Tree Trim
- New Tools that provide Instant Gratification – EVB/Field programmer to discuss various design stages.
- Video to show how to burn parts using a header even after parts are on a board
11:15 Demo 2: Program your own part using ClockBuilderPro Field Programmer
11:45 Concluding Remarks